A type of commercially available flash memory product is a MirrorBit® memory device available from Spansion, LLC, located in Sunnyvale, Calif. A MirrorBit cell effectively doubles the intrinsic density of a flash memory array by storing two physically distinct bits on opposite sides of a memory cell. Each bit within a cell can be programmed with a binary unit of data (either a logic one or zero) that is mapped directly to the memory array.
An exemplary MirrorBit® memory device 10, illustrated in FIG. 1, includes a P-type semiconductor substrate 12 within which are formed spaced-apart source/drain regions 14, 16 respectively (both typically having N-type conductivity), otherwise known as bit lines. A charge trapping layer or stack 18 is disposed on the top surface of the substrate between the bit lines. The charge trapping stack 18 typically comprises, for example, a charge trapping layer, often a silicon nitride layer 20, disposed between a first or bottom silicon dioxide layer (commonly referred to as a tunnel oxide layer) 22 and a second or top silicon dioxide layer 24. A gate electrode 26, which typically comprises an N or N+ polycrystalline silicon layer, is formed over the charge trapping stack to form a first storage element or bit 28 and a second storage element or bit 30 of memory cells 32 and 34. The charge trapping layer 20 of first storage bit 28 and the charge trapping layer 20 of second storage bit 30 of each memory cell 32 and 34 can be integral, as illustrated in FIG. 1, or can be separated by an isolation element, which typically is an oxide often referred to as a gate oxide.
A dual bit memory cell 34 is programmed utilizing a hot electron injection technique. More specifically, programming of the first bit 28 of memory cell 34 comprises injecting electrons into the charge trapping layer 20 and applying a bias between bit lines 14 and 16 while applying a high voltage to the control gate 26. In an exemplary embodiment, this may be accomplished by grounding bit line 16 and applying approximately 5 V to bit line 14 and approximately 10 V to the control gate 26. The voltage on the control gate 26 inverts a channel region 36 while the bias accelerates electrons from bit line 14 into the channel region 36 towards bit line 16. The 4.5 eV to 5 eV kinetic energy gain of the electrons is more than sufficient to surmount the 3.1 eV to 3.5 eV energy barrier at channel region 36/tunnel oxide layer 22 interface and, while the electrons are accelerated towards source/drain region 16, the field caused by the high voltage on control gate 26 redirects the electrons towards the charge trapping layer of first bit 28. Those electrons that cross the interface into the charge trapping layer remain trapped for later reading.
Similarly, programming the second bit 30 by hot electron injection into the charge trapping layer 20 comprises applying a bias between bit lines 16 and 14 while applying a high voltage to the control gate 26. This may be accomplished by grounding bit line 14 and applying approximately 5V to bit line 16 and approximately 10 V to the control gate 26. The voltage on the control gate 26 inverts the channel region 36 while the bias accelerates electrons from bit line 16 into the channel region 36 towards bit line 14. The field caused by the high voltage on control gate 26 redirects the electrons towards the charge trapping layer of second bit 30. Those electrons that cross the interface into charge trapping layer 20 of second bit 30 remain trapped for later reading.
With advances in semiconductor process technology, the trend is toward smaller and smaller semiconductor devices, including memory devices. However, as the-above described MirrorBit® is scaled smaller in size, transient program disturb (TPD) becomes a bigger challenge. TPD results during programming of the dual bit devices. For example, hot holes generated during programming of first bit 28 of memory cell 32 have a secondary impact ionization below bit line 16. Secondary electrons resulting from the secondary impact ionization diffuse to the disturbed cell 34 below gate 26 where they are accelerated by the drain depletion region and injected into the charge trapping stack 18 of second bit 30. This injection of secondary electrons into second bit 30 of cell 34 can adversely affect the memory window of bit 30.
Accordingly, it is desirable to provide a flash memory device with reduced transient program disturb. In addition, it is desirable to provide methods for fabricating flash memory devices with reduced transient program disturb. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.